urface temperature failures are among the most avoidable reasons a product fails certification. They are also among the most expensive to fix once a physical prototype exists. Most engineers understand that standards impose limits on how hot a product can get. Far fewer treat heat as a deliberate design parameter from the schematic stage onward.
The limits themselves are well established. IEC 62368-1 Clause 9 classifies thermal energy into three classes (TS1, TS2, and TS3) based on burn injury risk. For household appliances, IEC 60335-1 Clause 11 sets temperature rise limits for accessible surfaces by material type. What neither standard tells you is how to stay under those limits through deliberate engineering choices. That is what this article covers.
The approach here is design-first: component selection and power budgeting, then PCB layout, then enclosure strategy, then a pre-compliance checklist so you walk into the test lab with confidence. For the limits themselves and how they are measured, see our article on temperature limits in product design.
Start at the Schematic: Building a Power Budget for Thermal Compliance
The single most powerful tool for thermal compliance is a power budget. Before any PCB layout begins, list every component that dissipates meaningful power alongside three values: worst-case power dissipation, maximum junction temperature rating, and junction-to-ambient thermal resistance (Theta-JA) or junction-to-case resistance (Theta-JC).
This exercise routinely exposes problems that no layout or enclosure redesign can fix later. Finding them at the schematic level costs nothing to fix.
Power dissipation values come from the component datasheet. The relevant parameters are:
- Switching and conduction losses for MOSFETs
- I²R losses for resistors
- Forward-voltage drop multiplied by current for diodes
- Core and winding losses for inductors and transformers
Adding these values across all components defines the total thermal load. Your thermal system must carry that load into the surrounding environment within the margins set by your target standard.
How to Calculate Junction Temperature
This core relationship is straightforward. For any component, junction temperature equals ambient temperature plus power dissipation multiplied by thermal resistance:
T_junction = T_ambient + (P_dissipated × Theta-JA)
Consider a component with a Theta-JA of 50 °C/W dissipating 2 W at a 40 °C ambient. Junction temperature reaches 140 °C. If the component is rated to 125 °C, there is a compliance and reliability problem before the PCB has been laid out. The options are to derate the component, select a lower Theta-JA alternative, or plan explicitly for a heatsink, thermal pad, or forced airflow.
Tip: For components near the thermal limit, target a junction temperature no higher than 80% of the rated maximum under worst-case conditions. Datasheet ratings assume specific test conditions that may not match your application. A component running at its absolute maximum rated temperature has no derating margin. This will attract scrutiny from the test lab under IEC 60335-1 Clause 11 evaluations.
Account for Ambient Temperature Range
IEC 62368-1 thermal measurements run at 25 °C ambient. Your product, however, may carry a certification for use up to 40 °C or higher. Available headroom for internal dissipation shrinks as ambient rises. A product that passes at 25 °C can fail at 40 °C if the design ignores this from the start.
PCB Layout: Where Thermal Compliance Is Won or Lost
The PCB is the primary heat transport mechanism between components and the rest of the thermal system. A poor layout adds tens of degrees to junction temperatures and creates surface hotspots that no enclosure can fully compensate for. The four areas below have the largest thermal impact.
Copper Pour and Ground Plane Continuity
Copper is an excellent thermal conductor. Large copper pours on bottom and inner layers serve as heat spreaders as well as electrical references. Keep thermal vias and copper fills beneath high-dissipation components continuous and uninterrupted by signal routing. Fragmented ground planes force heat into narrow copper paths and concentrate hotspots.
For multi-layer boards, the thermal return path from a power component should reach adjacent copper pours through a dense via array directly under the package.
Via Stitching Under Power Components
Components in exposed-pad packages (QFNs, DFNs, DrMOS devices) require a grid of thermal vias connecting the exposed pad to the copper pour below. IPC-7093 provides guidance on via-in-pad designs that fill vias to prevent solder voiding. Voiding in a via array significantly degrades the thermal path.
A typical array for a 5 W QFN uses 16 to 25 vias of 0.3 mm diameter on a 0.8 mm pitch. Under-specified via arrays are a common cause of overtemperature failures that pass simulation but fail in hardware.
Trace Width for Current-Carrying Conductors
High-current traces heat up through resistive losses. Consult IPC-2152 during layout for any trace carrying more than 1 A. Running a 3 A trace sized for 1 A creates a local heat source. That heat adds to the thermal burden on nearby components and raises surface temperatures in the enclosure above.
Component Placement for Thermal Isolation
Place high-dissipation components away from thermally sensitive devices: precision references, oscillators, and battery protection ICs. Clustering multiple power-dissipating components creates a local heat island that is very difficult to manage at the enclosure level. Distribute dissipation across the board where the application allows.
Orient components so that natural convection within the enclosure carries heat away from critical areas, not into them.
Note: Ground plane and thermal design decisions overlap directly with EMC. A fragmented ground plane introduced for thermal routing can create conducted emissions problems. Always review thermal via placement and copper fills alongside your EMC layout strategy. Our article on ground plane and earth reference in EMC design covers the relationship between ground plane decisions and compliance outcomes in detail.
Enclosure and Ventilation Design for Surface Temperature Compliance
Once the PCB thermal strategy is set, the enclosure must complete the thermal path from board surface to the outside environment. It is simultaneously your thermal management tool and the surface measured during compliance testing. Its design directly determines whether the product passes or fails.
Thermal Resistance of Plastic Enclosure Walls
Plastic enclosures act as thermal insulators. The temperature drop across the wall depends on thickness, material conductivity, and available dissipation area. For a product with significant internal dissipation and no ventilation, surface temperature can exceed internal air temperature by tens of degrees.
ABS, PC, and PC/ABS alloys have thermal conductivities of 0.17 to 0.25 W/(m·K). That is roughly 1,000 times lower than aluminium. Passive cooling through a sealed plastic enclosure becomes extremely difficult above a few watts of total dissipation.
Natural Ventilation Openings
Ventilation slots allow hot air to exit and cooler air to enter without mechanical assistance. For effective natural convection, inlet openings go low on the enclosure and outlet openings go high. Total open area must match the thermal load.
JEITA guidelines and thermal management supplier application notes offer passive ventilation sizing rules. A basic simulation using the Boussinesq approximation can verify whether a slot arrangement will keep internal air below the threshold for surface temperature compliance.
Safety Requirements for Ventilation Openings
Enclosure openings introduce additional constraints under IEC 62368-1 and IEC 60335-1. Openings must not allow insertion of standard test probes to live or moving parts. Designers must also size them to prevent foreign object ingress per the applicable IP rating requirements.
Opening size is therefore a balance: ventilation adequacy on one side, safety compliance on the other.
Heatsinks and Thermal Interface Materials
For components dissipating above approximately 2 to 3 W in a passively cooled product, a heatsink is often necessary. A heatsink attached to the enclosure wall can function as a combined dissipation and heat-spreading surface.
When a heatsink forms part of the external product surface, compliance testing measures its temperature directly against the material-specific limits. Metal surfaces carry higher allowable touch temperatures than plastic under IEC 62368-1 Table 38 (2nd Ed.), due to differences in skin heat transfer coefficient. Even so, that surface remains a measured compliance point and your thermal model must include it.
Be careful: Never rely on bare metal-to-metal contact without a thermal interface material (TIM). Interface resistance without a TIM is unpredictable, highly sensitive to surface finish and contact pressure, and varies between units. Use TIM datasheets to include interface resistance values in your model.
Tip: When targeting IEC 62368-1 compliance, remember that Clause 9 thermal measurements run at 25 °C ambient. Surface temperatures under single fault conditions must not exceed TS2 limits for the relevant material. Design your enclosure with single fault scenarios in mind: identify which component failure produces the highest internal power dissipation, then verify that accessible surfaces stay within TS2 limits under that condition.
Pre-Compliance Thermal Testing: Check Before You Certify
An internal thermal characterization before formal testing identifies failures in your own lab, where changes are fast and inexpensive. The following checklist covers the minimum scope for a meaningful pre-compliance thermal evaluation.
These are the five steps to follow:
- Confirm test setup conditions. Match the requirements of your target standard: correct mains voltage (typically nominal +10%), ambient temperature at 25 °C for IEC 62368-1 Clause 9 measurements, and product positioned as it will be during use, including any orientation restrictions.
- Instrument before stabilisation. Attach surface thermocouples at all locations likely to be measured in formal testing: top surface, accessible sides, ventilation outlet areas. Add internal air thermocouples near the highest-dissipation components and component-mounted thermocouples at junction cases where package geometry permits.
- Run to thermal stabilisation. Operate the product at full rated load until all channels stabilise. Stabilisation is defined as a temperature change of less than 1 °C over a 15-minute period.
- Compare against limits. Check every measured value against surface temperature limits by material type, component maximum operating temperatures from datasheets with derating applied, and insulation temperature class limits for any wound components.
- Simulate fault conditions. Run the most likely single fault conditions identified in your risk analysis. Record which fault produces the highest surface temperatures.
For thermocouple selection and attachment technique in appliance testing, the IEC 60335-1 thermocouple placement guide and the thermocouple types and placement article cover the practical details.
Treat any reading that exceeds 90% of the applicable limit as a failure risk and address it before formal testing. A 5 °C margin between your worst-case internal reading and the standard limit is not conservative. Thermal measurement uncertainty, test setup variation between labs, and unit-to-unit component variation can each account for that margin individually.
The pre-compliance stage is also the right moment to review your leakage current design. Thermal and electrical safety choices interact: components added to control leakage current affect power dissipation, and thermal protection devices influence the electrical safety architecture. Our article on leakage current design and mitigation strategies covers this interaction in full.
Note: IEC 62368-1 sub-clause 5.4.1.4 specifies maximum operating temperatures for materials and components under normal operating conditions. These are separate from the touch temperature limits in Clause 9. Your product must satisfy both sets of limits simultaneously. A product that passes touch temperature limits at the surface can still fail if an internal insulation material exceeds its rated temperature class.
Frequently Asked Questions
What is the difference between TS1, TS2, and TS3 in IEC 62368-1? These are thermal energy classes describing the hazard level at a touchable surface. TS1 surfaces are unlikely to cause pain during brief contact; TS2 may cause pain but not injury; TS3 can cause injury and requires a safeguard or warning.
How do I calculate junction temperature from a component datasheet? Multiply the component’s power dissipation in watts by its junction-to-ambient thermal resistance Theta-JA in °C/W, then add the maximum expected ambient temperature. If the result exceeds 80% of the rated maximum junction temperature, the component needs derating or better thermal management.
Does IEC 62368-1 require thermal testing at 40 °C ambient? No. Clause 9 thermal measurements run at 25 °C ambient. The manufacturer’s specified maximum ambient (Tma) is used for other aspects of the standard, but not for setting the touch temperature limits in Table 38.
What via array is needed under a QFN for good thermal performance? A common starting point is 70 to 80% coverage of the exposed pad area, using vias of approximately 0.3 mm diameter on a 0.8 mm pitch. Always verify against the component’s land pattern recommendation and thermal design notes in its datasheet.
When should I use a thermal interface material instead of direct contact? Always. Bare metal-to-metal contact produces unpredictable interface resistance that varies with surface finish and contact force. Even a low-performance TIM reduces this variability substantially and lowers the interface resistance between units.
Conclusion
Thermal compliance is an engineering outcome, not a testing outcome. The decisions that determine whether a product passes surface temperature limits are made at three stages: the schematic (power budget and component selection), the PCB layout (thermal path continuity, via stitching, trace sizing), and the enclosure design (ventilation, wall conductivity, heatsink integration).
By the time a product reaches a formal test lab, the thermal outcome is largely already set. A structured pre-compliance measurement campaign, comparing results against IEC 62368-1 Clause 9 and IEC 60335-1 Clause 11 limits, gives you the opportunity to find and fix problems on your own terms, at your own pace. Build the thermal model early, verify it in hardware before the compliance date, and the test lab becomes a confirmation rather than a surprise.
